Modern integrated circuits are among the most complex objects humans have ever built. A leading-edge chip contains over 100 billion transistors in an area smaller than a fingernail. Here is how it gets made.
1. Starting with Silicon Silica — silicon dioxide from quartz sand — is chemically reduced to produce nearly pure silicon. It is then melted at 1,414°C and slowly grown into a single-crystal ingot using the Czochralski process. This ingot is sliced into thin wafers, polished to atomic flatness.
2. Photolithography The circuit pattern is transferred onto the wafer using light. A photosensitive material called photoresist is coated onto the wafer. A mask — containing the circuit layout — blocks UV or EUV light in precise patterns. Where light hits, the resist changes chemically, allowing etching below.
EUV (Extreme Ultraviolet) lithography uses 13.5 nm wavelength light, enabling features as small as 2–3 nm. ASML is currently the only company that makes EUV scanners.
3. Doping Pure silicon is a poor conductor. To make it useful, impurities (dopants) are implanted using ion beams. Phosphorus or arsenic create n-type regions (extra electrons). Boron creates p-type regions (holes). Together they form transistors — the basic switching element.
4. Deposition and Etching Thin films of metals (copper, tungsten), insulators (silicon dioxide, hafnium oxide), and semiconductors are deposited using CVD or ALD processes — some just a few atoms thick. Between each layer, plasma etching removes material with nanometer precision.
5. Interconnects Transistors are connected by up to 15 metal layers, each separated by insulating dielectrics. The routing problem — connecting billions of transistors with minimal resistance and crosstalk — is solved by EDA software running for weeks on server farms.
6. Testing and Packaging Every die on the wafer is electrically tested. Failing dies are marked and discarded. Good dies are cut, bonded to substrates, underfilled with epoxy, and packaged. Advanced 3D packages like TSMC's CoWoS or Intel's Foveros stack chips vertically for density and bandwidth.
The entire process takes 3–4 months and involves over 1,000 individual manufacturing steps.